Power is one of the biggest challenges facing the semiconductor industry because every generation of CPU uses about twice as much power as the previous one. Researchers are exploring new ideas at various design stages to solve this issue. While we believe that most of the existing ideas in low power VLSI design are valid, we also need to focus on how we sample the external objects, extract the features, and process the data. Here, we provide a completely different approach to low power design. We start from the mixed signal data collection and integrate the sampling scheme with memory and digitization. This integrated interface model will reduce the data amount at the very beginning of data acquisition. Thus, data received at the CPU, as well as power consumption in the CPU, will be greatly reduced.
For every generation of high end CPU, the power consumption increases by 2×. While we scale down transistor feature size, our processors are also becoming less power/energy efficient. So where does the energy go? Bill Daily in his recent talk [1] pointed out that “data movement”, “driving long wires”, “accessing arrays” and “control overhead” are the four major factors that caused energy waste in CPUs. One solution he suggested was stream computing. IBM's Cell processor is one such solution. Viewed as a major breakthrough in image processing for game console development in 2005, the Cell processor demonstrated 197 Gb/s data flow at 3.2 GHz for a Synergistic Processing Unit (SPU) [2][3] with 70 W average power consumption. This allows high definition display for computer entertainment systems in real time.
Stream computing is not limited to game consoles, computers and servers. Thanks to a rapid growth of wired or wireless sensors for various applications, CPU and processors have been applied as part of the data acquisition systems in a number of areas including communication, military tracking and monitoring, health care, physical/biology/chemical experiments, environmental testing, and transportation carriers [2].
FIG. 5 shows a diagram for a typical data acquisition system. It has a sensor with analog mixed signal front end and stream processor. The performance of these two components is very different. Most analog front ends consume 2/3 of the total chip area. While the power consumption is in the μW to mW range, the ability to sample and process data is a lot slower than digital processors. For example, a typical 24 bit ADC at Texas Instruments [4] is capable of 125 k sps (sample per second) which leads to 3 Mbps data processing speed. With 197 Gb/s of cell processor SPU, the analog front end is several orders of magnitude slower. This means that with the current stream processor capability, we can consider real time control of the analog front end to obtain “useful” samples. The term “useful” samples refer to the most important information embedded in the samples.
Traditional data acquisition systems discard a lot of data right before it is transmitted. In contrast, this invention presents a new architecture that is data/information oriented and allows us to reduce the amount of data from the very beginning. FIG. 6 demonstrates a proposed architecture for the new data acquisition system. Note that the data is reduced at the analog front end, thus the stream processor receives only a fraction of the total amount of original data. With a reduced amount of data, less energy will be consumed in “data movement”, “driving long wires”, “accessing arrays” and “control overhead” in the stream processors.
Any feature or combination of features described herein are included within the scope of the present invention provided that the features included in any such combination are not mutually inconsistent as will be apparent from the context, this specification, and the knowledge of one of ordinary skill in the art. Additional advantages and aspects of the present invention are apparent in the following detailed description and claims.